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AAT3242 Datasheet(PDF) 2 Page - Advanced Analog Technology, Inc. |
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AAT3242 Datasheet(HTML) 2 Page - Advanced Analog Technology, Inc. |
2 / 16 page AAT3242 300mA/150mA Dual CMOS LDO Linear Regulator 2 3242.2006.04.1.10 Pin Descriptions Pin Configuration TSOPJW-12 (Top View) 1 2 3 4 5 6 12 11 10 9 8 7 ENA GND GND POKA OUTB INB INA OUTA POKB GND GND ENB Pin # Symbol Function 1 ENA Enable Regulator A pin; this pin should not be left floating. When pulled low, the PMOS pass transistor turns off and the device enters shutdown mode, consuming less than 1µA. 2, 3, 8, 9 GND Ground connection pins. 4 POKA Power OK pin with open drain output. It is pulled low when the OUTA pin is below the 10% regulation window. 5 OUTB Low current (150mA) regulator output pin; should be decoupled with a 2.2µF or greater output low-ESR ceramic capacitor. 6 INB Input voltage pin for Regulator B; should be decoupled with 1µF or greater capacitor. 7 ENB Enable Regulator B; this pin should not be left floating. When pulled low, the PMOS pass transistor turns off and the device enters shutdown mode, con- suming less than 1µA. 10 POKB Power OK pin with open drain output. It is pulled low when the OUTB pin is below the 10% regulation window. 11 OUTA High-current (300mA) regulator output pin; should be decoupled with a 2.2µF or greater output low-ESR ceramic capacitor. 12 INA Input voltage pin for Regulator A; should be decoupled with 1µF or greater capacitor. |
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