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SY100S318FCTR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100S318FCTR Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 6 page 1 SY100S318 Micrel, Inc. M9999-032206 hbwhelp@micrel.com or (408) 955-1690 BLOCK DIAGRAM D1a D2a D3a D4a D5a D1b D2b D3b D4b O O D1c D2c D3c D4c D1d D2d D3d D4d D1e D2e SY100S318 5-WIDE 5, 4, 4, 4, 2 OA/OAI GATE FEATURES DESCRIPTION Pin Function Dna – Dne Data Inputs (n = 1...5) O – O Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs PIN NAMES Rev.: H Amendment: /0 Issue Date: March 2006 s Max. propagation delay of 800ps s IEE min. of –55mA s Extended supply voltage option: VEE = –4.2V to –5.5V s Voltage and temperature compensation for improved noise immunity s Internal 75K Ω input pull-down resistors s 70% faster than Fairchild s 40% lower power than Fairchild s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages The SY100S318 is an ultra-fast 5-wide 5, 4, 4, 4, 2 OR/ AND gate with both true and complementary outputs, designed for use in high-performance ECL systems. The inputs on this device have 75K Ω pull-down resistors. |
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