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SY100S317FCTR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100S317FCTR Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 6 page 1 SY100S317 Micrel, Inc. M9999-032206 hbwhelp@micrel.com or (408) 955-1690 SY100S317 TRIPLE 2-WIDE OA/OAI GATE DESCRIPTION The SY100S317 is a set of ultra-fast, triple 2-wide OR/ AND gates designed for use in high-performance ECL systems. This device offers both true and complement outputs. The inputs on this device have 75K Ω pull-down resistors. s Max. propagation delay of 900ps s IEE min. of –48mA s Extended supply voltage option: VEE = –4.2V to –5.5V s Voltage and temperature compensation for improved noise immunity s Internal 75K Ω input pull-down resistors s Approximately 40% lower power than Fairchild s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages FEATURES Rev.: H Amendment: /0 Issue Date: March 2006 BLOCK DIAGRAM D1a Oa Oa D2a D3a D4a Ea D1b Ob Ob D2b D3b D4b Eb D1c Oc Oc D2c D3c D4c Ec Pin Function Dna – Dnc Data Inputs (n = 1...4) Ea – Ec Enable Inputs Oa – Oc Data Outputs Oa – Oc Complementary Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs PIN NAMES |
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