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SY10H602JZTR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY10H602JZTR Datasheet(HTML) 1 Page - Micrel Semiconductor |
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1 / 4 page  1 SY10H602 SY100H602 Micrel, Inc. M9999-032906 hbwhelp@micrel.com or (408) 955-1690 Pin Function GND TTL Ground (0V) VCCE ECL VCC (0V) VCCO ECL VCC (0V) — Outputs VCCT TTL Supply (+5.0V) VEE ECL Supply (–5.2/–4.5V) D0–D8 Data Inputs (TTL) Q0–Q8 Data Outputs (ECL) ENECL Enable Control (ECL) LEN Latch Enable (ECL) MR Master Reset (ECL) DESCRIPTION FEATURES s 9-bit ideal for byte-parity applications s Flow-through configuration s Extra TTL and ECL power/ground pins to minimize switching noise s Dual supply s 3.5ns max. D to Q s PNP TTL inputs for low loading s Choice of ECL compatibility: MECL 10KH (10Hxxx) or 100K (100Hxxx) s Fully compatible with MC10H/100H602 s Available in 28-pin PLCC package The SY10/100H602 are 9-bit, dual supply TTL-to-ECL translators with latches. Devices in the Micrel 9-bit translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance. The H602 features D-type latches. Latching is controlled by Latch Enable (LEN), while the Master Reset input resets the latches. A post-latch logic enable is also provided (ENECL), allowing control of the output state without destroying latch data. All control inputs are ECL level. The 10H version is compatible with MECL 10KH ECL logic levels. The 100H version is compatible with 100K levels. SY10H602 SY100H602 9-BIT LATCHED TTL-TO-ECL Rev.: E Amendment: /0 Issue Date: March 2006 BLOCK DIAGRAM Q0 D0 TTL LEN MR ECL Q D EN Q1 D1 Q D EN Q2 D2 Q D EN Q3 D3 Q D EN Q4 D4 Q D EN Q5 D5 Q D EN Q6 D6 Q D EN Q7 D7 Q D EN Q8 D8 Q D EN ENECL PIN NAMES |
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