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SY10H606JC Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY10H606JC Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 5 page 1 SY10H606 SY100H606 Micrel, Inc. M9999-032906 hbwhelp@micrel.com or (408) 955-1690 Pin Function D0 – D5 TTL Data Inputs CLK, CLK Differential PECL Clock Inputs TCLK TTL Clock Input MR PECL Master Reset Input Q0 – Q5 True PECL Outputs Q0 – Q5 Inverted PECL Outputs VCCE PECL VCC (5.0V) VCCT TTL VCC (5.0V) GND TTL/PECL Ground VBB VBB Reference Output (PECL) DESCRIPTION FEATURES The SY10/100H606 are 6-bit, registered, single supply TTL-to-PECL translators. The devices feature differential PECL outputs as well as a choice between either a differential PECL clock input or a TTL clock input. The asynchronous master reset control is a PECL level input. With its differential ECL outputs and TTL inputs, the H606 device is ideally suited for the transmit function of a HPPI bus-type board-to-board interface application. The on-chip registers simplify the task of synchronizing the data between the two boards. The device is available in either ECL standard: the 10H device is compatible with 10K logic levels, while the 100H device is compatible with 100K logic levels. BLOCK DIAGRAM SY10H606 SY100H606 Rev.: E Amendment: /0 Issue Date: March 2006 PIN NAMES DQ R CLK Dn CLK TCLK CLK Qn Qn MR VBB 1 OF 6 BITS REGISTERED HEX TTL-TO-PECL s Differential 50 Ω ECL outputs s Choice between differential PECL or TTL clock input s Single +5V power supply s VBB output for single-ended use s Multiple power and ground pins to minimize noise s Specified within-device skew s Fully compatible with MC10H/100H606 s Available in 28-pin PLCC package |
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