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SY10EP451LTGTR Datasheet(PDF) 4 Page - Micrel Semiconductor |
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SY10EP451LTGTR Datasheet(HTML) 4 Page - Micrel Semiconductor |
4 / 10 page Micrel, Inc. SY10/100EP451L March 2007 4 M9999-030507-A hbwhelp@micrel.com or (408) 955-1690 Pin Description Pin Number Pin Name Pin Function 2, 3 32, 1 30, 31 26, 27 24, 25 22, 23 D0, /D0 D1, /D1 D2, /D2 D3, /D3 D4, /D4 D5, /D5 ECL Differential Data Inputs: These input pairs are the different data signal inputs to the device. Each input pin is connected to a 75k Ω pull-down resistor. Due to an internal clamping circuit, D will default LOW and /D will default HIGH if left open. 29 MR ECL Master Reset Input pin. If input pin is left open, it will default to LOW. 4, 5 CLK, /CLK ECL Differential Clock Input: This input pair is the clock signal input to the device. Each input pin is connected to a 75k Ω pull-down resistor. Due to an internal clamping circuit, CLK will default LOW and /CLK will default HIGH if left open. 7, 8 9, 10 11, 12 14, 15 17, 18 20, 21 Q0, /Q0 Q1, /Q1 Q2, /Q2 Q3, /Q3 Q4, /Q4 Q5, /Q5 ECL Differential Data Outputs: Q defaults to LOW and /Q defaults to HIGH if D inputs are left open. See “LVPECL Output Interface Applications” section for recommendations on terminations. 6, 13, 16 VCC Positive Supply: Bypass with 0.1 µF||0.01µF low ESR capacitors as close to the VCC pins as possible. 19, 28 VEE Negative Power Supply: VEE must be tied to most negative supply. |
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