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SY100E446JZ Datasheet(PDF) 7 Page - Micrel Semiconductor |
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SY100E446JZ Datasheet(HTML) 7 Page - Micrel Semiconductor |
7 / 9 page 7 SY10E446 SY100E446 Micrel, Inc. M9999-032206 hbwhelp@micrel.com or (408) 955-1690 APPLICATIONS INFORMATION The SY10E/100E446 are integrated 4:1 parallel-to-serial converters. The chips are designed to work with the E445 device to provide both transmission and receiving of a high- speed serial data path. The E446 can convert 4 bits of data into a 1.3Gb/s NRZ data stream. The device features a SYNC input which allows the user to reset the internal clock circuitry and restart the conversion sequence (see Timing Diagram A). Note that SOUT is triggered by negative clock edges. The E446 features a differential serial input and internal divide-by-eight circuitry to facilitate the cascading of two devices to build an 8:1 multiplexer. Figure 1 illustrates the architecture for an 8:1 multiplexer using two E446s (see Timing Diagram B). Notice the serial outputs (SOUT) of the lower order converter feed the serial inputs of the higher order device. This feed through of the serial inputs bounds the upper end of the frequency of operation. The clock-to- serial output propagation delay, plus the set-up time of the serial input pins, must fit into a single clock period for the cascade architecture to function properly. Using the worst case values for these two parameters from the data sheet, tPD CLK to SOUT = 1600ps and ts for SIN = –200ps, yields a minimum period of 1400ps or a clock frequency of 700MHz. The clock frequency is somewhat lower than that of a single converter. In order to increase this frequency, it is recommended that the clock edge feeding the E446A be delayed with respect to the E446B, as shown in Figure 2. Perhaps the easiest way to delay the second clock relative to the first is to take advantage of the differential clock inputs of the E446. By connecting the clock for E446A to the complimentary clock input pin, the device will clock a half a clock period after E446B (Figure 2). Utilizing this simple technique will raise the potential conversion frequency up to the maximum 1.3GHz of a stand-alone E446. Figure 1. Cascaded 8:1 Converter Architecture E446B SOUT SOUT D3 D2 D1 D0 D7 D6 D5 D4 E446A SOUT SOUT D3 D2 D1 D0 D3 D2 D1 D0 SIN SIN CLK CLK SERIAL DATA PARALLEL DATA 1400ps 200ps CLK tPD CLK to SOUT 1600ps |
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