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SY100E451JI Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100E451JI Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 4 page 1 SY10E451 SY100E451 Micrel, Inc. M9999-032206 hbwhelp@micrel.com or (408) 955-1690 6-BIT REGISTER DIFFERENTIAL DATA CLOCK DESCRIPTION The SY10/100E451 offer six D-type flip-flops with single- ended outputs and differential data and clock inputs, designed for use in new, high-performance ECL systems. The registers are triggered by the rising edge of the CLK input. A logic HIGH on the Master Reset (MR) input resets all outputs to a logic LOW. The VBB output is provided for use as a reference voltage for single-ended reception of ECL signals to that device only. When used for this purpose, it is recommended that VBB is decoupled to VCC via a 0.01µF capacitor. FEATURES s 1100MHz min. toggle frequency s Extended 100E V EE range of –4.2V to –5.5V s Differential inputs: data and clock s V BB output for single-ended use s Asynchronous Master Reset s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K Ω input pulldown resistors s Fully compatible with Motorola MC10E/100E451 s Available in 28-pin PLCC package SY10E451 SY100E451 BLOCK DIAGRAM D R D R D R D R D R D R Q0 Q1 Q2 Q3 Q4 Q5 MR D0 D1 D2 D3 D4 D5 VBB CLK /D0 /CLK /D1 /D2 /D3 /D4 /D5 Pin Function D0–D5 + Data Input /D0–/D5 – Data Input CLK + Clock Input /CLK – Clock Input Q0–Q5 Data Outputs MR Master Reset Input VBB VBB Output VCCO VCC to Output PIN NAMES Rev.: G Amendment: /0 Issue Date: March 2006 |
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