SN74V215, SN74V225, SN74V235, SN74V245

512

× 18, 1024 × 18, 2048 × 18, 4096 × 18

DSP-SYNC

 FIRST-IN, FIRST-OUT MEMORIES

SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002

18

POST OFFICE BOX 655303

Data Write 1

Data Write 2

Data Read

Data In Output Register

WCLK

D0–D17

EF

WEN

RCLK

OE

REN

Q0–Q17

tDS

tDS

tENS

tENH

tENS

tENH

tSKEW1

tFRL

(see Note A)

tFRL

(see Note A)

tSKEW1

tREF

tREF

tREF

Low

tA

NOTES: A. When tSKEW1 is at the minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 is less than the minimum

specification, tFRL (maximum) = either (2 × tCLK) + tSKEW1 or tCLK + tSKEW1. The latency timing applies only at the empty

boundary (EF is low).

B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.

Figure 6. Single Register-Buffered Empty Flag Timing (Standard Mode)