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U6813B Datasheet(PDF) 5 Page - ATMEL Corporation

Part No. U6813B
Description  Fail-safe IC with High-side and Relay Driver
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Maker  ATMEL [ATMEL Corporation]
Homepage  http://www.atmel.com
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U6813B Datasheet(HTML) 5 Page - ATMEL Corporation

 
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5
4543B–AUTO–10/05
U6813B
4.1
WDI Input (Pin 11)
The microcontroller has to provide a trigger signal with the frequency f
WDI which is fed to the WDI
input. A positive edge of f
WDI detected by a slope detector resets the binary counter and clocks
the up/down counter.The latter one counts only from 0 to 3 or reverse. Each correct trigger
increments the up/down counter by 1, each wrong trigger decrements it by 1. As soon as the
counter reaches status 3, the RS flip-flop is set; see Figure 4-3 (Watchdog state diagram). A
missing incoming trigger signal is detected after 250 clocks of the internal watchdog frequency
f
RC (see WD_OK output) and resets the up/down counter directly.
4.2
WDC Input (Pin 10)
It is to be equiped by external R/C components. By means of an external R/C circuitry, the IC
generates a time base (frequency f
WDC) independent from the microcontroller. The watchdog’s
time window refers to a frequency of f
WDC = 100 × fWDI.
4.3
OSCERR Input
A smart watchdog has to ensure that internal problems with its own time base are detected and
do not lead to an undesired status of the complete system. If the RC oscillator stops oscillating,
a signal is fed to the OSCERR input after a time-out delay. It resets the up/down counter and
disables the WD-OK output. Without this reset function, the watchdog would freeze its current
status when f
RC stops.
4.4
RESET Input
During power-on and under/overvoltage detection, a reset signal is fed to this pin. It resets the
watchdog timer and sets the initial state.
4.5
WD-OK Output
After the up/down counter has reached to status 3 (see Figure 4-3, Watchdog State Diagram),
the RS flip-flop is set and the WD-OK output becomes logic “1”. As WD-OK is directly connected
to the enable pins, the open-collector output P-EN provides also logic “1” while a logic “0” is
available at N-EN output. If on the other hand the up/down counter is decremented to “0”, the RS
flip-flop is reset, the WD-OK output and the P-EN output are logic “0” and N-EN output is logic
“1”. The WD-OK output also controls a dual MUX stage which shifts the time window by one
clock after a successful trigger, thus forming a hysteresis to provide stable conditions for the
evaluation of the trigger signal “good or false”. The WD-OK signal is also reset in case the
watchdog counter is not reset after 250 clocks (missing trigger signal).
Figure 4-2.
Watchdog Timing Diagram with Tolerances
Time/s
79/ f
WDC
80/ f
WDC
169/ f
WDC
170/ f
WDC
250/ f
WDC
251/ f
WDC
Watchdog Window
update rate is good
Update rate is
too fast
Update rate is
either too fast or
good
Update rate is
either too slow
or good
Update rate is
too slow
Update rate is
either too slow
or pulse has
dropped out
Pulse has
dropped out


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