Electronic Components Datasheet Search |
|
SY100E337JC Datasheet(PDF) 1 Page - Micrel Semiconductor |
|
SY100E337JC Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 5 page 1 SY10E337 SY100E337 Micrel, Inc. M9999-032206 hbwhelp@micrel.com or (408) 955-1690 FEATURES s 1500ps max. clock to bus (data transmit) s 1000ps max. clock to Q (data receive) s Extended 100E VEE range of –4.2V to –5.5V s 25 Ω cutoff bus outputs s 50 Ω receiver outputs s Scannable implementation of E336 s Synchronous and asynchronous bus enables s Non-inverting data path s Bus outputs feature internal edge slow-down capacitors s Additional package ground pins s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K Ω input pulldown resistors s Fully compatible with Motorola MC10E/100E337 s Available in 28-pin PLCC package 3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER DESCRIPTION The SY10/100E337 are 3-bit registered bus transceivers with scan designed for use in new, high- performance ECL systems. The bus outputs (BUS0–BUS2) are designed to drive a 25 Ω bus; the receive outputs (Q0–Q2) are designed for 50 Ω. The bus outputs feature a normal logic HIGH level (VOH) and a cutoff LOW level of –2.0V and the output emitter-follower is “off”, presenting a high impedance to the bus. The bus outputs also feature edge slow-down capacitors. Both drive and receive sides feature the same logic, including a loopback path to hold data. The LOAD/HOLD function is controlled by Transmit Enable (TEN) and Receive Enable (REN) on the transmit and receive sides, respectively, with a HIGH selecting LOAD. The implementation of the E337 Receive Enable differs from that of the E336. A synchronous bus enable (SBUSEN) is provided for normal, non-scan operation. The asynchronous bus disable (ABUSDIS) disables the bus for scan mode. The SYNCEN input allows either synchronous or asynchronous re-enabling after disabling with ABUSDIS. An alternative use is asynchronous-only operation with ABUSDIS, in which case SYNCEN is tied LOW. SYNCEN is implemented as an overriding SET control to the enable flip-flop. Scan mode is selected by a logic HIGH at the SCAN input. Scan input data is shifted in through S-IN, and output data appears at the Q2 output. All registers are clocked on the rising edge of CLK. Additional lead-frame grounding is provided through the ground pins (GND) which should be connected to 0V. The GND pins are not electrically connected to the chip. SY10E337 SY100E337 Pin Function A0–A2 Data Inputs A B0–B2 Data Inputs B S-IN Serial (Scan) Data Input TEN, REN LOAD/HOLD Controls SCAN Scan Control ABUSDIS Asynchronous Bus Disable SBUSEN Synchronous Bus Enable SYNCEN Synchronous Enable Control CLK Clock BUS0–BUS2 25 Ω Cutoff BUS Outputs Q0–Q2 Receive Data Outputs (Q2 serves as SCAN_OUT in scan mode) VCCO VCC to Output PIN NAMES Rev.: F Amendment: /0 Issue Date: March 2006 |
Similar Part No. - SY100E337JC |
|
Similar Description - SY100E337JC |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |