UJA1069TW24 datasheet(9/64 Pages) PHILIPS

Part #	UJA1069TW24

Description	LIN fail-safe system basis chip

Download	64 Pages

Scroll/Zoom	100%

Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

Logo

9 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

9 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

6.2.1 Start-up mode

Start-up mode is the ‘home page’ of the SBC. This mode is entered when battery and

ground are connected for the ﬁrst time. Start-up mode is also entered after any event that

results in a system reset. The reset source information is provided by the SBC to support

different software initialization cycles that depend on the reset event.

It is also possible to enter Start-up mode via a wake-up from Standby mode, Sleep mode

or Fail-safe mode. Such a wake-up can originate either from the LIN-bus or from the local

WAKE pin.

On entering Start-up mode a lengthened reset time tRSTNL is observed. This reset time is

either user-deﬁned (via the RLC bit in the System Conﬁguration register) or defaults to the

value as given in Section 6.12.12. During the reset lengthening time pin RSTN is held

LOW by the SBC.

When the reset time is completed (pin RSTN is released and goes HIGH) the watchdog

timer will wait for initialization. If the watchdog initialization is successful, the selected

operating mode (Normal mode or Flash mode) will be entered. Otherwise the Restart

mode will be entered.

6.2.2 Restart mode

The purpose of the Restart mode is to give the application a second chance to start up,

should the ﬁrst attempt from Start-up mode fail. Entering Restart mode will always set the

reset lengthening time tRSTNL to the higher value to guarantee the maximum reset length,

regardless of previous events.

If start-up from Restart mode is successful (the previous problems do not reoccur and

watchdog initialization is successful), then the selected operating mode will be entered.

From Restart mode this must be Normal mode. If problems persist or if V1 fails to start up,

then Fail-safe mode will be entered.

6.2.3 Fail-safe mode

Severe fault situations will cause the SBC to enter Fail-safe mode. Fail-safe mode is also

entered if start-up from Restart mode fails. Fail-safe mode offers the lowest possible

system power consumption from the SBC and from the external components controlled by

the SBC.

A wake-up (via the LIN-bus or the WAKE pin) is needed to leave Fail-safe mode. This is

only possible if the on-chip oscillator is running correctly. The SBC restarts from Fail-safe

mode with a deﬁned delay tret, to guarantee a discharged V1 before entering Start-up

mode. Regulator V1 will restart and the reset lengthening time tRSTNL is set to the higher

value; see Section 6.5.1.

6.2.4 Normal mode

Normal mode gives access to all SBC system resources, including LIN, INH/LIMP and

EN. Therefore in Normal mode the SBC watchdog runs in (programmable) Window mode,

for strictest software supervision. Whenever the watchdog is not properly served a system

reset is performed.

Similar Part No. - UJA1069TW24

Manufacturer	Part #	Datasheet	Description
NXP Semiconductors	UJA1069TW24	310Kb / 64P	LIN fail-safe system basis chip Rev. 03-10 September 2007
NXP Semiconductors	UJA1069TW24	304Kb / 64P	LIN fail-safe system basis chip Rev. 04-28 October 2009

More results

Similar Description - UJA1069TW24

Manufacturer	Part #	Datasheet	Description
NXP Semiconductors	UJA1069	304Kb / 64P	LIN fail-safe system basis chip Rev. 04-28 October 2009
	UJA1069	310Kb / 64P	LIN fail-safe system basis chip Rev. 03-10 September 2007
	UJA1065	285Kb / 67P	High-speed CAN/LIN fail-safe system basis chip Rev. 01-10 August 2005
	UJA1061	340Kb / 74P	Fault-tolerant CAN/LIN fail-safe system basis chip Rev. 05-22 November 2007
	UJA1065	470Kb / 76P	High-speed CAN/LIN fail-safe system basis chip Rev. 07-25 February 2010
	UJA1061	529Kb / 77P	Fault-tolerant CAN/LIN fail-safe system basis chip Rev. 06-9 March 2010
	UJA1066	473Kb / 70P	High-speed CAN fail-safe system basis chip Rev. 03-17 March 2010
	PF5030_SDS	354Kb / 20P	Fail-safe system basis chip with multiple SMPSs and LDOs Rev. 1 - 22 November 2022
	FS8600-SDS	527Kb / 15P	Fail-safe system basis chip with multiple SMPSs and LDOs Rev. 1.1-23 November 2021
	FS8600_SDS	243Kb / 16P	Fail-safe system basis chip with multiple SMPSs and LDOs Rev. 2.0 - 7 December 2022

More results

UJA1069TW24 Datasheet(PDF) 9 Page - NXP Semiconductors

UJA1069TW24 Datasheet(HTML) 9 Page - NXP Semiconductors

Similar Part No. - UJA1069TW24

Similar Description - UJA1069TW24

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL