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SY10E101JYTR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY10E101JYTR Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 4 page 1 SY10E101 SY100E101 Micrel, Inc. M9999-032006 hbwhelp@micrel.com or (408) 955-1690 s 500ps max. propagation delay s Extended 100E VEE range of –4.2V to –5.5V s True and complementary outputs s Fully compatible with industry standard 10KH, 100K I/O levels s Internal 75K Ω input pulldown resistors s Fully compatible with Motorola MC10E/100E101 s Available in 28-pin PLCC package QUAD 4-INPUT OR/NOR GATE The SY10/100E101 are quad 4-input OR/NOR gates designed for use in new, high-performance ECL systems. The E101 features both true and complementary outputs. SY10E101 SY100E101 FEATURES DESCRIPTION BLOCK DIAGRAM Pin Function Dna, Dnb, Dnc, Dnd Data Inputs Q0-Q3 True Outputs Q0-Q3 Inverting Outputs VCCO VCC to Output PIN NAMES Rev.: G Amendment: /0 Issue Date: March 2006 |
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