NTB65N02RG datasheet(1/8 Pages) ONSEMI

Part #	NTB65N02RG

Description	Power MOSFET 65 A, 24 V N-Channel TO-220, D2PAK

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Manufacturer	ONSEMI [ON Semiconductor]

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May, 2005 − Rev. 6

1

Publication Order Number:

NTB65N02R/D

NTB65N02R, NTP65N02R

Power MOSFET

65 A, 24 V N−Channel

TO−220, D2PAK

Features

• Planar HD3e Process for Fast Switching Performance

• Low R

DSon to Minimize Conduction Loss

• Low C

iss to Minimize Driver Loss

• Low Gate Charge

• Pb−Free Packages are Available*

MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified)

Parameter

Symbol

Value

Unit

Drain−to−Source Voltage

VDSS

25

Vdc

Gate−to−Source Voltage − Continuous

VGS

±20

Vdc

Thermal Resistance − Junction−to−Case

Total Power Dissipation @ TC = 25°C

Drain Current −

Continuous @ TC = 25°C, Chip

Continuous @ TC =25°C, Limited by Package

Single Pulse (tp = 10 ms)

RqJC

PD

ID

IDM

2.0

62.5

65

58

160

°C/W

W

A

Thermal Resistance −

Junction−to−Ambient (Note 1)

Total Power Dissipation @ TA = 25°C

Drain Current − Continuous @ TA = 25°C

RqJA

PD

ID

67

1.86

10

°C/W

W

A

Thermal Resistance −

Junction−to−Ambient (Note 2)

Total Power Dissipation @ TA = 25°C

Drain Current − Continuous @ TA = 25°C

RqJA

PD

ID

120

1.04

7.6

°C/W

W

A

Operating and Storage Temperature Range

TJ and

Tstg

−55 to

150

°C

Single Pulse Drain−to−Source Avalanche

Energy − Starting TJ = 25°C

(VDD = 50 Vdc, VGS = 10 Vdc, IL = 11 Apk,

L = 1 mH, RG = 25 W)

EAS

60

mJ

Maximum Lead Temperature for Soldering

Purposes, 1/8

″ from Case for 10 Seconds

TL

260

°C

Maximum ratings are those values beyond which device damage can occur.

Maximum ratings applied to the device are individual stress limit values (not

normal operating conditions) and are not valid simultaneously. If these limits are

exceeded, device functional operation is not implied, damage may occur and

reliability may be affected.

1. When surface mounted to an FR4 board using 1 in. pad size, (Cu Area 1.127 in2).

2. When surface mounted to an FR4 board using minimum recommended pad

size, (Cu Area 0.412 in2).

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

AYWW

P65N02RG

http://onsemi.com

TO−220AB

CASE 221A

STYLE 5

MARKING

DIAGRAMS

65N02R = Specific Device Code

A

= Assembly Location

Y

= Year

WW

= Work Week

G

= Pb−Free Package

D2PAK

CASE 418AA

STYLE 2

D

S

G

AYWW

65N02RG

1

2

3

4

1

2

3

4

24 V

8.4 m

W @ 10 V

RDS(on) TYP

65 A

ID MAX

V(BR)DSS

PIN ASSIGNMENT

1

FUNCTION

Gate

2

Drain

3

Source

4

Drain

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

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