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T89C51RD2-RLFCM Datasheet(PDF) 7 Page - ATMEL Corporation

Part # T89C51RD2-RLFCM
Description  0 to 40 MHz Flash Programmable 8-bit Microcontroller
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

T89C51RD2-RLFCM Datasheet(HTML) 7 Page - ATMEL Corporation

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7
T89C51RD2
4243G–8051–05/03
12
14
8
I
INT0 (P3.2): External interrupt 0
13
15
9
I
INT1 (P3.3): External interrupt 1
14
16
10
I
T0 (P3.4): Timer 0 external input
15
17
11
I
T1 (P3.5): Timer 1 external input
16
18
12
O
WR (P3.6): External data memory write strobe
17
19
13
O
RD (P3.7): External data memory read strobe
Reset
9
10
4
I/O
Reset: A high on this pin for two machine cycles while the oscillator is running, resets
the device. An internal diffused resistor to V
SS permits a power-on reset using only an
external capacitor to VCC. This pin is an output when the hardware watchdog forces a
system reset.
ALE/PROG
30
33
27
O (I)
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for
external timing or clocking. Note that one ALE pulse is skipped during each access to
external data memory. This pin is also the program pulse input (PROG) during Flash
programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE
will be inactive during internal fetches.
PSEN
29
32
26
O
Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
EA
31
35
29
I
External Access Enable: EA must be externally held low to enable the device to fetch
code from external program memory locations 0000H to FFFFH (RD). If security level
1 is programmed, EA will be internally latched on Reset.
XTAL1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
XTAL2
18
20
14
O
Crystal 2: Output from the inverting oscillator amplifier
Table 2. Pin Description (Continued)
Mnemonic
Pin Number
Type
Name and Function
DIL
LCC
VQFP 1.4


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