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AT83C5103XXX-ICSAL Datasheet(PDF) 25 Page - ATMEL Corporation |
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AT83C5103XXX-ICSAL Datasheet(HTML) 25 Page - ATMEL Corporation |
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25 / 64 page  25 AT8xC5103 4134C–8051–09/04 Reset Value = 00010100b Serial Peripheral Status Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions: • Data transfer complete • Write collision • Inconsistent logic level on SS pin (mode fault error) Table 12 describes the SPSTA register and explains the use of every bit in the register. Reset Value = 00X0XXXXb 0 SPR0 R/W 100: FCLK PERIPH /32 101: FCLK PERIPH /64 110: FCLK PERIPH /128 111: Don’t Use Bit Number Bit Mnemonic R/W Mode Description Table 12. SPSTA: Serial Peripheral Status and Control Register - SPSTA (S:C4h) 76 543210 SPIF WCOL SSERR MODF - - - - Bit Number Bit Mnemonic R/W Mode Description 7 SPIF R Serial Peripheral Data Transfer Flag Clear by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. Set by hardware to indicate that the data transfer has been completed. 6WCOL R Write Collision Flag Cleared by hardware to indicate that no collision has occurred or has been approved by a clearing sequence. Set by hardware to indicate that a collision has been detected. 5 SSERR R Synchronous Serial Slave Error Flag Set by hardware when SS is deasserted before the end of a received data. Cleared by disabling the SPI (clearing SPEN bit in SPCON). 4MODF R Mode Fault Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been approved by a clearing sequence. Set by hardware to indicate that the SS pin is at inappropriate logic level 3- R/W Reserved The value read from this bit is indeterminate. Do not set this bit. 2- R/W Reserved The value read from this bit is indeterminate. Do not set this bit. 1- R/W Reserved The value read from this bit is indeterminate. Do not set this bit. 0- R/W Reserved The value read from this bit is indeterminate. Do not set this bit. |
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