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AT26F004 Datasheet(PDF) 12 Page - ATMEL Corporation |
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AT26F004 Datasheet(HTML) 12 Page - ATMEL Corporation |
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12 / 38 page  12 3588C–DFLASH–04/06 AT26F004 8.4 Chip Erase The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase command can be started, the Write Enable command must have been pre- viously issued to the device to set the WEL bit of the Status Register to a logical “1” state. Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the device will erase the entire memory array. The erasing of the device is internally self-timed and should take place in a time of t CHPE. The complete opcode must be clocked into the device before the CS pin is deasserted; other- wise, no erase will be performed. In addition, if any sector of the memory array is in the protected state, then the Chip Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if a sector is in the protected state. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Regis- ter be polled rather than waiting the t CHPE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state. Figure 8-5. Chip Erase SCK CS SI SO MSB 23 1 0 CCCCCCCC 67 5 4 OPCODE HIGH-IMPEDANCE |
Similar Part No. - AT26F004_06 |
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Similar Description - AT26F004_06 |
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