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NCV7361A Datasheet(PDF) 12 Page - ON Semiconductor

Part No. NCV7361A
Description  Voltage Regulator with Integrated LIN Transceiver
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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NCV7361A Datasheet(HTML) 12 Page - ON Semiconductor

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NCV7361A
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12
Normal Mode
Sleep Mode
Normal Mode
POR
UVR
POR
UVR
EN = H/L
Figure 16. Operating of Power On and Undervoltage RESET
VSUP
VSUVR_OFF
VSUVR_ON
VOUT
Switching into sleep mode can be done independently
from the current transceiver state. That means if the
transmitter is in dominant state this state will be cancelled
and it will be switched to recessive state.
POR−state
This is the power−on−reset state of the NCV7361A,
while VSUP < VSUVR_OFF. If the prior state was sleep mode,
the NCV7361A switches via the Ini−state to normal mode.
Ini−state
This is an intermediate state, which will pass through
after switch−on of VSUP or VOUT. The NCV7361A remains
in this state if VOUT is below VRES (Reset Output = L) and
VSUP > VSUVR_ON.
Thermal Shutdown
If the junction temperature TJ is higher than TJSHD
(>155
°C), the NCV7361A will be switched into the
thermal shutdown mode. The behavior within this mode is
comparable with the sleep mode except for LIN transceiver
operating. The transceiver is completely disabled, no
wake−up functionality is available.
If TJ falls below the thermal recovery temperature TJREC
(typical 140
°C) the NCV7361A will be recover to the
previous state (normal or sleep).
Initialization
Initialization is started if the power supply is switched on
as well as every rising edge on of the NCV7361A via the
EN pin.
VSUP − Power On
If VSUP is switched on the NCV7361A starts to normal
mode via the POR− and Ini−state. A combination of
dynamic POR and undervoltage reset circuitry generates a
POR signal, which switches the NCV7361A into normal
mode. This power on behavior is independent from the
status of the EN pin.
Power−on−Reset and
undervoltage
reset
operates
independent
from
each
other,
which
secures
the
independence from the rise time of VSUP. During fast VSUP
edges the Power−on−Reset will be active. If the increasing
of VSUP is very slow (> 1 ms/V) the undervoltage reset unit
initializes the voltage regulator if VSUP > VSUVR_OFF
(typical 3.5 V).
The effects of both POR circuits at different VSUP slopes
as shown in Figure 16.
After POR the voltage regulator starts and VOUT will be
output. If VOUT > VMRes the bus interface will be activated.
If the VOUT voltage level is higher than VRES, the reset time
tRes = 100 ms is started. After tRes the RESET output
switches from low to high (Figure 16).
Start of Linear Regulator via Wake−Up
The initialization is only being done for the VOUT
circuitry parts. This procedure begins with leaving the
master reset state (VOUT > VMRes) and runs in the same
manner as the VSUP − Power−On.
Wake−Up
If the regulator is put into sleep mode it can be
“waked−up” with the BUS interface. Every pulse on the
BUS (high pulse or low pulse) with a pulse width of
minimum 60
ms switches on the regulator.
After the BUS has “waked−up” the regulator, it can only
be switched off with a high level followed by a low level
on the EN pin.
VSUP Undervoltage Reset
The undervoltage detection unit inhibit an undefined
behavior of the NCV7361A under low voltage condition.
If VSUP drops below VSUVR_ON (typical 3 V) the
undervoltage detection becomes active and the IC will be
switched to POR state. The following increasing of VSUP
above VSUVR_OFF (typical 3.5 V) cancels this POR state
and the voltage regulator starts with the initialization
sequence.
VSUP Undervoltage in Normal Mode
Supply Voltages below VSUVR_OFF do not influence the
voltage regulator. The output voltage VOUT follows VSUP.


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