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AT34C02B-10TU-1.7 Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT34C02B-10TU-1.7 Datasheet(HTML) 7 Page - ATMEL Corporation |
7 / 21 page 7 AT34C02B 3417E–SEEPR–1/07 Figure 2. Bus Timing SCL: Serial Clock SDA: Serial Data I/O Figure 3. Write Cycle Timing SCL: Serial Clock SDA: Serial Data I/O Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Figure 4. Data Validity twr (1) STOP CONDITION START CONDITION WORDn ACK 8th BIT SCL SDA |
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