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AT43USB353M Datasheet(PDF) 5 Page - ATMEL Corporation

Part No. AT43USB353M
Description  Low Cost Full-speed USB Microcontroller with Embedded Hub, ADC and PWM
Download  95 Pages
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Maker  ATMEL [ATMEL Corporation]
Homepage  http://www.atmel.com
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AT43USB353M Datasheet(HTML) 5 Page - ATMEL Corporation

 
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5
AT43USB353M
3307B–USB–4/04
The embedded USB hardware of the AT43USB353M is a compound device, consisting of a 3
port hub with a permanently attached function on one port. The hub and attached function are
two independent USB devices, each having its own device addresses and control end-points.
The hub has its dedicated interrupt end-point, while the USB function has 3 additional pro-
grammable end-points with separate FIFOs. Two of the FIFOs are 64 bytes deep and the third
is 8 bytes deep.
Depending on the state of the CPUSEL input pin, device pin 43, the MCU runs at 12 MHz or
24 MHz. The clock that operates the MCU is generated by the USB hardware. While at
12 MHz the nominal and average period of the clock is 83.3 ns. It may have single cycles that
deviate by ±20.8 ns during a phase adjustment by the SIE's clock/data separator of the USB
hardware. The 24 MHz clock runs with a clock period of 41.67 ns that may increase to 62.5 ns
for one cycle when the SIE's clock/data separator makes an adjustment. The clock frequen-
cies of the various modules of the AT43USB353M is summarized in Table 1.
Note:
Refer to page 15 for details of the on chip oscillator and PLL.
The microcontroller shares most of the control and status registers of the megaAVR Microcon-
troller Family. The registers for managing the USB operations are mapped into its SRAM
space. The I/O section on page 13 summarizes the available I/O registers. The “AVR Register
Set” on page 32 covers the AVR registers. Please refer to the Atmel AVR manual for more
information.
The fast-access register file concept contains 32 x 8-bit general-purpose working registers
with a single clock cycle access time. This means that during one single clock cycle, one Arith-
metic Logic Unit (ALU) operation is executed. Two operands are output from the register file,
the operation is executed, and the result is stored back in the register file – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing - enabling efficient address calculations. One of the three address pointers
is also used as the address pointer for look-up tables in program memory. These added func-
tion registers are the 16-bit X-, Y- and Z-registers.
The ALU supports arithmetic and logic operations between registers or between a constant
and a register. Single register operations are also executed in the ALU. Figure 2 on page 4
shows the AT43USB353M AVR Enhanced RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used
on the register file as well. This is enabled by the fact that the register file is assigned the 32
lowest Data Space addresses ($00 - $1 F), allowing them to be accessed as though they were
ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, Timer/Counters, and other I/O functions. The I/O Memory can be accessed directly, or as
the Data Space locations following those of the register file, $20 - $5F.
The AVR uses a Harvard architecture concept – with separate memories and buses for pro-
gram and data. The program memory is executed with a single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program memory is
a downloadable SRAM or a mask programmed ROM.
Table 1. Module Clock Frequencies
CPUSEL Pin
MCU Clock
Timer/Counter Clock
ADC Clock
WDT Clock
0
24 MHz
12 MHz
1 MHz
1 MHz
1
12 MHz
12 MHz
1 MHz
1 MHz


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