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AT43USB353M Datasheet(PDF) 45 Page - ATMEL Corporation |
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AT43USB353M Datasheet(HTML) 45 Page - ATMEL Corporation |
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45 / 95 page  45 AT43USB353M 3307B–USB–4/04 value, but the down-counting compare match is not interpreted to be reached before the next time the counter reaches the TOP value, making a one-period PWM pulse. Note: X = A or B In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from $0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode, i.e. it is executed when TOV1 is set provided that Timer Overflow Interrupt1 and global interrupts are enabled. This also applies to the Timer Output Compare1 flags and interrupts. Watchdog Timer The Watchdog Timer is clocked from a 1 MHz clock derived from the 6 MHz on chip oscillator. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted, see Table 20 for a detailed description. The WDR (Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog reset, the AT43USB355 resets and executes from the reset vector. To prevent unintentional disabling of the watchdog, a special turn-off sequence must be fol- lowed when the watchdog is disabled. Refer to the description of the Watchdog Timer Control Register for details. Figure 14. Watchdog Timer Table 19. PWM Outputs OCR1X = $0000 or Top COM1X1 COM1X0 OCR1X Output OC1X 1 0 $0000 L 10 TOP H 1 1 $0000 H 11 TOP L 1 MHz Clock MCU Reset WDE WDP2 WDP1 WDP0 Watchdog Reset Watchdog Prescaler |
Similar Part No. - AT43USB353M_04 |
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Similar Description - AT43USB353M_04 |
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