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ATMEGA8535-16MI Datasheet(PDF) 54 Page - ATMEL Corporation |
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ATMEGA8535-16MI Datasheet(HTML) 54 Page - ATMEL Corporation |
54 / 321 page 54 ATmega8535(L) 2502K–AVR–10/06 ceeding positive clock edge. As indicated by the two arrows t pd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 25. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay t pd through the synchronizer is one system clock period. Figure 25. Synchronization when Reading a Software Assigned Pin Value out PORTx, r16 nop in r17, PINx 0xFF 0x00 0xFF SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17 t pd |
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