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ATMEGA644_0702 Datasheet(PDF) 90 Page - ATMEL Corporation |
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ATMEGA644_0702 Datasheet(HTML) 90 Page - ATMEL Corporation |
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90 / 374 page  90 2593L–AVR–02/07 ATmega644 The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen- erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See Section “13.4” on page 91. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request. 13.1.2 Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com- pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. The definitions in Table 13-1 are also used extensively throughout the document. 13.2 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres- caler, see ”Timer/Counter Prescaler” on page 154. 13.3 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 13-2 shows a block diagram of the counter and its surroundings. Figure 13-2. Counter Unit Block Diagram Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. Table 13-1. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is depen- dent on the mode of operation. DATA BUS TCNTn Control Logic count TOVn (Int.Req.) Clock Select top Tn Edge Detector ( From Prescaler ) clk Tn bottom direction clear |
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