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NCP5425DBR2G Datasheet(PDF) 21 Page - ON Semiconductor

Part # NCP5425DBR2G
Description  Dual Synchronous Buck Controller
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP5425DBR2G Datasheet(HTML) 21 Page - ON Semiconductor

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NCP5425
http://onsemi.com
21
EMI MANAGEMENT
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise
during normal operation. When designing for compliance
with EMI/EMC regulations, additional components may be
necessary to reduce noise emissions. These components are
not required for regulator operation and experimental results
may allow them to be eliminated. The input filter inductor
may not be required because bulk filter and bypass
capacitors, as well as other loads located on the board will
tend to reduce regulator di/dt effects on the circuit board and
input power supply. Placement of the power components to
minimize routing distance will also help to reduce
emissions.
LAYOUT GUIDELINES
When laying out a buck regulator on a printed circuit
board, the following checklist should be used to ensure
proper operation of the NCP5425.
1. Rapid changes in voltage across parasitic capacitors
and abrupt changes in current in parasitic inductors
are major concerns.
2. Keep high currents out of sensitive ground
connections.
3. Avoid ground loops as they pick up noise. Use star
or single point grounding.
4. For high power buck regulators on double−sided
PCB’s a single ground plane (usually the bottom)
is recommended.
5. Even though double sided PCB’s are usually
sufficient for a good layout, four−layer PCB’s are
the optimum approach to reducing susceptibility to
noise. Use the two internal layers as the power and
GND planes, the top layer for power connections
and component vias, and the bottom layers for the
noise sensitive traces.
6. Keep the inductor switching node small by placing
the output inductor, switching and synchronous
FETs close together.
7. The MOSFET gate traces to the IC must be short,
straight, and wide as possible.
8. Use fewer, but larger output capacitors, keep the
capacitors clustered, and use multiple layer traces
with wide, thick copper to keep the parasitic
resistance low.
9. Place the switching MOSFET as close to the input
capacitors as possible.
10. Place the output capacitors as close to the load as
possible.
11. Place the COMP capacitor as close as possible to
the COMP pin.
12. Connect the filter components of pins ROSC, VFB,
VOUT, and COMP, to the GND pin with a single
trace, and connect this local GND trace to the
output capacitor GND.
13. Place the VCC bypass capacitors as close as possible
to the IC.
14. Place the ROSC resistor as close as possible to the
ROSC pin.
15. Assign the output with lower duty cycle to
channel 2, which has inherently better noise
immunity.


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