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NCP5425DBR2G Datasheet(PDF) 13 Page - ON Semiconductor

Part # NCP5425DBR2G
Description  Dual Synchronous Buck Controller
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP5425DBR2G Datasheet(HTML) 13 Page - ON Semiconductor

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NCP5425
http://onsemi.com
13
DESIGN GUIDELINES
General
The output voltage tolerance can be affected by any or all
of the following:
1. Buck regulator output voltage set point accuracy.
2. Output voltage change due to discharging or
charging of the bulk decoupling capacitors during
a load current transient.
3. Output voltage change due to the ESR and ESL of
the bulk and high frequency decoupling capacitors,
circuit traces, and vias.
4. Output voltage ripple and noise.
Budgeting the tolerance is left to the designer who must
consider all of the above effects and provide an output
voltage that will meet the specified tolerance at the load. The
designer must also ensure that the regulator component
temperatures are kept within the manufacturer’s specified
ratings at full load and maximum ambient temperature.
Selecting Feedback Divider Resistors
VOUT
R1
R2
VFB
Figure 9. Feedback Divider Resistors
The feedback pins (VFB1(2)) are connected to external
resistor dividers to set the output voltages. The error
amplifier is referenced to 0.8 V and the output voltage is
determined by selecting resistor divider values. Resistor R1
is selected based on a design trade−off between efficiency
and output voltage accuracy. The output voltage error
resulting from the bias current of the error amplifier can be
estimated, neglecting resistor tolerance, from the following
equation:
%Error
+ (100)(1
10−6)(R1) 0.8
Rearranging, R1
+ (%Error)(0.8) (1
10−4)
After R1 has been chosen, R2 can be calculated from:
R2
+ (R1) ((VOUT 0.8 V) * 1)
Example:
Assume the desired VOUT = 1.2 V, and the tolerable error
due to input bias current is 0.2%.
R1
+ (0.2)(0.8) (1
10−4)
+ 1.6 K
R2
+ 1.6 K ((1.2 0.8) * 1) + 1.6 K 0.5 + 3.2 K
Calculating Duty Cycle
The duty cycle of a buck converter (including parasitic
losses) is given by the formula:
Duty Cycle
+ D +
VOUT ) (VHFET ) VL)
VIN ) VLFET + VHFET + VL
where:
VOUT = buck regulator output voltage;
VHFET = high side FET voltage drop due to RDS(ON);
VL = output inductor voltage drop due to inductor wire
DC resistance;
VIN = buck regulator input voltage;
VLFET = low side FET voltage drop due to RDS(ON).
Switching Frequency Select and Set
Selecting the switching frequency is a trade−off between
component size and power losses. Operation at higher
switching frequencies allows the use of smaller inductor and
capacitor values. Nevertheless, it is common to select lower
frequency operation because a higher frequency also
diminishes efficiency due to MOSFET gate charge losses.
Additionally, low value inductors at higher frequencies
result in higher ripple current, higher output voltage ripple,
and lower efficiency at light load currents. The value of the
oscillator resistor is designed to be linearly related to the
switching period. If the designer prefers not to use Figure 10
to select the appropriate resistance, the following equation
is a suitable alternative:
ROSC +
21700
* fSW
2.31 fSW
where:
ROSC = oscillator resistor in kW;
fSW = switching frequency in kHz.
Figure 10. Switching Frequency vs. ROSC
800
700
600
500
400
300
200
100
10
20
30
40
50
60
ROSC (kW)
70
0


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