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NCP5422A Datasheet(PDF) 5 Page - ON Semiconductor

Part No. NCP5422A
Description  Dual Out−of−Phase Synchronous Buck Controller with Current Limit
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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NCP5422A Datasheet(HTML) 5 Page - ON Semiconductor

 
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NCP5422A, NCP5423
http://onsemi.com
5
ELECTRICAL CHARACTERISTICS (0
°C < TA < 70°C; 0°C < TJ < 125°C; ROSC = 30.9 k, CCOMP1,2 = 0.1 mF,
10.8 V < VCC < 13.2 V; 10.8 V < BST < 20 V, CGATE(H)1,2 = CGATE(L)1,2 = 1.0 nF, unless otherwise specified.)
Characteristic
Unit
Max
Typ
Min
Test Conditions
Supply Currents
VCC Current
COMP1,2 = 0 V (No Switching)
13
17
mA
BST Current
COMP1,2 = 0 V (No Switching)
3.5
6.0
mA
Undervoltage Lockout
Start Threshold
GATE(H) Switching; COMP1,2 charging
7.8
8.6
9.4
V
Stop Threshold
GATE(H) not switching; COMP1,2 discharging
7.0
7.8
8.6
V
Hysteresis
Start−Stop
0.5
0.8
1.5
V
Hiccup Mode Overcurrent Protection
OVC Comparator Offset Voltage
0 V < IS+ 1(2) < 5.5 V, 0 V < IS− 1(2) < 5.5 V
55
70
85
mV
Discharge Threshold
0.20
0.25
0.30
V
IS+ 1(2) Bias Current
0 V < IS+ 1(2) < 5.5 V
−1.0
0.1
1.0
mA
IS− 1(2) Bias Current
0 V < IS− 1(2) < 5.5 V
−1.0
0.1
1.0
mA
OVC Common Mode Range
Note 3
0
5.5
V
OVC Latch COMP1 Discharge Current
COMP1 = 1.0 V
2.0
5.0
8.0
mA
OVC Latch COMP2 Discharge Current
COMP2 = 1.0 V
0.3
1.2
3.5
mA
COMP1 Charge/Discharge Ratio in OVC
5.0
6.0
7.0
3. Guaranteed by design, not 100% tested in production.
PACKAGE PIN DESCRIPTION
PIN NO.
PIN SYMBOL
FUNCTION
1
GATE(H)1
High Side Switch FET driver pin for channel 1.
2
GATE(L)1
Low Side Synchronous FET driver pin for channel 1.
3
GND
Ground pin for all circuitry contained in the IC. This pin is internally bonded to the substrate of the IC.
4
BST
Power input for GATE(H)1 and GATE(H)2 pins.
5
IS+1
Positive input for channel 1 overcurrent comparator.
6
IS−1
Negative input for channel 1 overcurrent comparator.
7
VFB1
Error amplifier inverting input for channel 1.
8
COMP1
Channel 1 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error
Amp compensation. The same capacitor provides Soft−Start timing for channel 1. This pin also
disables the channel 1 output when pulled below 0.3 V.
9
COMP2
Channel 2 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error
Amp compensation and Soft−Start timing for channel 2. Channel 2 output is disabled when this pin is
pulled below 0.3 V.
10
VFB2
Error amplifier inverting input for channel 2.
11
IS−2
Negative input for channel 2 overcurrent comparator.
12
IS+2
Positive input for channel 2 overcurrent comparator.
13
ROSC
Oscillator frequency pin. A resistor from this pin to ground sets the oscillator frequency.
14
VCC
Input Power supply pin.
15
GATE(L)2
Low Side Synchronous FET driver pin for channel 2.
16
GATE(H)2
High Side Switch FET driver pin for channel 2.


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