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AT25256W-10SJ-1.8 Datasheet(PDF) 9 Page - ATMEL Corporation |
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AT25256W-10SJ-1.8 Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 22 page 9 AT25128/256 0872O–SEEPR–03/05 The AT25128/256 is capable of a 64-byte page write operation. After each byte of data is received, the six-low order address bits are internally incremented by one; the high- order bits of the address will remain constant. If more than 64 bytes of data are transmit- ted, the address counter will roll over and the previously written data will be overwritten. The AT25128/256 is automatically returned to the write disable state at the completion of a write cycle. NOTE: If the device is not Write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS fall- ing edge is required to reinitiate the serial communication. Timing Diagrams (for SPI Mode 0 (0, 0)) Figure 3. Synchronous Data Timing Table 10. Address Key Address AT25128 AT25256 AN A13 - A0 A14 - A0 Don’t Care Bits A 15 - A14 A 15 SO V OH V OL HI-Z HI-Z t V VALID IN SI V IH V IL t H t SU t DIS SCK V IH V IL t WH t CSH CS V IH V IL t CSS t CS t WL t HO |
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