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AT90S8515-4JC Datasheet(PDF) 73 Page - ATMEL Corporation |
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AT90S8515-4JC Datasheet(HTML) 73 Page - ATMEL Corporation |
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73 / 112 page  73 AT90S8515 0841G–09/01 Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND The Port D Input Pins address (PIND) is not a register; this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read and when reading PIND, the logical values present on the pins are read. Port D as General Digital I/O PDn, general I/O pin: The DDDn bit in the DDRD register selects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PDn is set (one) when configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off the PDn has to be cleared (zero) or the pin has to be configured as an output pin. The Port D pins are tri- stated when a reset condition becomes active, even if the clock is not active. Note: n: 7,6…0, pin number. Alternate Functions of Port D • RD – Port D, Bit 7 RD is the external data memory read control strobe. See “Interface to External SRAM” on page 60 for detailed information. • WR – Port D, Bit 6 WR is the external data memory write control strobe. See “Interface to External SRAM” on page 60 for detailed information. • OC1A – Port D, Bit 5 OC1A: Output compare match output. The PD5 pin can serve as an external output when the Timer/Counter1 compare matches. The PD5 pin has to be configured as an output (DDD5 set [one]) to serve this function. See the Timer/Counter1 description for further details and how to enable the output. The OC1A pin is also the output pin for the PWM mode timer function. Bit 7 65 43 21 0 $12 ($32) PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 65 43 21 0 $11 ($31) DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 65 43 21 0 $10 ($30) PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND Read/Write RR RR RR RR Initial Value N/A N/A N/A N/A N/A N/A N/A N/A Table 24. DDDn Bits on Port D Pins DDDn PORTDn I/O Pull-up Comment 0 0 Input No Tri-state (high-Z) 0 1 Input Yes PDn will source current if ext. pulled low. 1 0 Output No Push-pull Zero Output 1 1 Output No Push-pull One Output |
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