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AT90S2313 Datasheet(PDF) 40 Page - ATMEL Corporation |
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AT90S2313 Datasheet(HTML) 40 Page - ATMEL Corporation |
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40 / 92 page  40 AT90S2313 0839I–AVR–06/02 EEPROM Control Register – EECR • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and will always read as zero. • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure. • Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal (EEWE) is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical “1” is writtentoEEWE, oth- erwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEAR (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical “1” to the EEMWE bit in EECR (to be able to write a logical “1” to theEEMWE bit, theEEWE bit must be writtentozerointhe same cycle). 5. Within four clock cycles after setting EEMWE, write a logical “1” to EEWE. When the write access time (typically 2.5 ms at V CC =5V or 4 ms at VCC =2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during the last four steps to avoid these problems. • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal (EERE) is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR Register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruc- tion is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O Registers, the write operation will be interrupted and the result is undefined. Bit 7654 3 2 1 0 $1C ($3C) –––– – EEMWE EEWE EERE EECR Read/Write R RRRR R/W R/W R/W Initial value 0000 0 0 0 0 |
Similar Part No. - AT90S2313_02 |
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Similar Description - AT90S2313_02 |
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