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NCP1212 Datasheet(PDF) 12 Page - ON Semiconductor

Part # NCP1212
Description  Current Mode PWM Controller for Both Forward and Flyback Converters
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP1212 Datasheet(HTML) 12 Page - ON Semiconductor

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NCP1212
http://onsemi.com
12
Current Sense Section
The current sense pin, CS detects the voltage drop across
a current sensing resistor, Rsense connected in between the
power MOSFET and Ground. In most cases, a narrow spike
on the leading edge of the current waveform can be observed
and may cause the power supply to exhibit an instability
when the output is lightly loaded. The spike is due to the
power transformer inter−winding capacitance and output
rectifier recovery time which are unavoidable. NCP1212
provides a 300 ns Leading Edge Blanking block to shield off
the spike. With the Leading Edge Blanking function, the CS
pin is not sensitive to the power switch turn−on noise and
spikes, practically in most applications, no filtering network
is required.
In normal operation, voltage developed at the current
sense input is compared with the level shifted control input
voltage and an internal Current Limit Threshold, VCS. In
case the CS input exceeds the Current Limit Threshold,
which is 1.0 V (typ.) in NCP1212, the gate driver output will
be forced to turn off immediately.
Thus the maximum allowable peak current is given by the
following equation:
Ipk(max) +
1V
Rsense
Soft−Start and Maximum Duty Selection
NCP1212 includes an internal Soft−Start function to
simplify designer’s job hence make this device easy to use.
During the startup phase, a constant current source of 8.0
mA
flows out of the SS/DMAX pin once VCC attains the
minimum startup voltage. The capacitor connected at
SS/DMAX pin is slowly charged up and the voltage
developed plus one diode drop, VSST is compared with the
saw−tooth waveform, CT from the internal oscillator as
shown in Figure 34. Whenever CT voltage is higher than
VSST, gate driver output will be turned off. Since VSST rises
slowly and it controls the output duty gradually increases as
shown in Figure 35. The minimum CT voltage is at 1.0 V,
hence there is no output before SS/DMAX pin attains about
0.4 V (1.0 V–1 diode drop). Soft−Start block will have no
effect to the PWM operation once VSST reaches 3.2 V.
Figure 34. Soft−Start Operation
S
Q
Q
+
F/F
Overload
Enable
Reset
+
3.2 V
From CT
Vsst
+5 V
8
mA
Shutdown
SS/DMAX
NCP1212
Duty Cycle Control
CSS
Figure 35. Output Pulse Duty Cycle Depends on the SS/DMAX Pin Voltage
VSST
VDRV
CT


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