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NCP1200 Datasheet(PDF) 10 Page - ON Semiconductor |
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NCP1200 Datasheet(HTML) 10 Page - ON Semiconductor |
10 / 16 page NCP1200 http://onsemi.com 10 Time Internal Fault Flag Time Time Drv VCC Driver Pulses Driver Pulses 11.4 V 9.8 V 6.3 V Regulation Occurs Here Latchoff Phase Fault is Relaxed Fault Occurs Here Startup Phase Figure 20. If the fault is relaxed during the VCC natural fall down sequence, the IC automatically resumes. If the fault persists when VCC reached UVLOL, then the controller cuts everything off until recovery. Calculating the VCC Capacitor As the above section describes, the fall down sequence depends upon the VCC level: how long does it take for the VCC line to go from 11.4 V to 9.8 V? The required time depends on the startup sequence of your system, i.e. when you first apply the power to the IC. The corresponding transient fault duration due to the output capacitor charging must be less than the time needed to discharge from 11.4 V to 9.8 V, otherwise the supply will not properly start. The test consists in either simulating or measuring in the lab how much time the system takes to reach the regulation at full load. Let’s suppose that this time corresponds to 6ms. Therefore a VCC fall time of 10 ms could be well appropriated in order to not trigger the overload detection circuitry. If the corresponding IC consumption, including the MOSFET drive, establishes at 1.5 mA, we can calculate the required capacitor using the following formula: Dt + DV @ C i , with DV = 2V. Then for a wanted Dt of 10 ms, C equals 8 mF or 10 mF for a standard value. When an overload condition occurs, the IC blocks its internal circuitry and its consumption drops to 350 mA typical. This appends at VCC = 9.8 V and it remains stuck until VCC reaches 6.5 V: we are in latchoff phase. Again, using the calculated 10 mF and 350 mA current consumption, this latchoff phase lasts: 109 ms. Protecting the Controller Against Negative Spikes As with any controller built upon a CMOS technology, it is the designer’s duty to avoid the presence of negative spikes on sensitive pins. Negative signals have the bad habit to forward bias the controller substrate and induce erratic behaviors. Sometimes, the injection can be so strong that internal parasitic SCRs are triggered, engendering irremediable damages to the IC if they are a low impedance path is offered between VCC and GND. If the current sense pin is often the seat of such spurious signals, the high−voltage pin can also be the source of problems in certain circumstances. During the turn−off sequence, e.g. when the user unplugs the power supply, the controller is still fed by its VCC capacitor and keeps activating the MOSFET ON and OFF with a peak current limited by Rsense. Unfortunately, if the quality coefficient Q of the resonating network formed by Lp and Cbulk is low (e.g. the MOSFET Rdson + Rsense are small), conditions are met to make the circuit resonate and thus negatively bias the controller. Since we are talking about ms pulses, the amount of injected charge (Q = I x t) immediately latches the controller which brutally discharges its VCC capacitor. If this VCC capacitor is of sufficient value, its stored energy damages the controller. Figure 21 depicts a typical negative shot occurring on the HV pin where the brutal VCC discharge testifies for latchup. |
Similar Part No. - NCP1200_06 |
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Similar Description - NCP1200_06 |
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