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NCP1028 Datasheet(PDF) 22 Page - ON Semiconductor |
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NCP1028 Datasheet(HTML) 22 Page - ON Semiconductor |
22 / 29 page NCP1028 http://onsemi.com 22 The principle consists in selecting the RR resistor, connected from pin 2 to ground, to impose a current IRR in the transistor collector. Figure 38. Maximum Peak Current Setpoint Variations versus Ramp Compensation The equation to get the right compensation level is the following: RR + Vp2.75 k Sa@TSW (eq. 9) where Vp, the total voltage swing, equals 2.75 V. Application example: Suppose we have the following flyback specifications: Vout = 5.0 V output voltage Vf = 1.0 V secondary diode forward drop @ Iout nominal Np:Ns = 1:N = 1:0.052 transformer turn ratio Lp = 3.8 mH primary inductance We can calculate the off slope, the one actually needed to evaluate Sa, by reflecting the output voltage over the primary inductance. The slope is projected over a complete switching period. Here, we use a 65 kHz part. Soff + Vout ) Vf NLp TSW + 6 15u 0.052 3.8m + 455 mA 15 ms (eq. 10) Due to the internal sense arrangement, this current slope will become a voltage slope having a value of: S off + 455m 0.375 + 170 mV 15 ms (eq. 11) If we chose 50% of this downslope, then the final compensation ramp will present a slope of: Sa + 170m 2 + 85 mV 15 ms (eq. 12) We then have: RR + Vp2.75 k Sa@TSW + 2.75 2.75k 85m + 89 kW (eq. 13) In the above calculations, the internal ESD resistor has purposely been omitted to avoid bringing in another variable. In case no ramp compensation is required, pin 2 must be tied to VCC, the adjacent pin. Soft−Start The NCP1028 features a 1.0 ms soft−start, which reduces the power−on stress, but also contributes to lower the output overshoot. Figure 39 shows a typical operating waveform. The NCP1028 features a novel patented structure which offers a better soft−start ramp, almost ignoring the startup pedestal inherent to traditional current−mode supplies. Figure 39. 1.0 ms Soft−Start Sequence |
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