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ATMEGA8-16PU Datasheet(PDF) 9 Page - ATMEL Corporation |
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ATMEGA8-16PU Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 23 page 9 ATmega8(L) 2486QS–AVR–10/06 Notes: 1. Refer to the USART description for details on how to access UBRRH and UCSRC. 2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 0x01 (0x21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 173 0x00 (0x20) TWBR Two-wire Serial Interface Bit Rate Register 171 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page |
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