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NCP346 Datasheet(PDF) 2 Page - ON Semiconductor |
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NCP346 Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 15 page NCP346 http://onsemi.com 2 Figure 2. Detailed Block Diagram − + CNTRL (3) OUT (1) GND (2) LOGIC BLOCK DRIVER Pre−regulator VCC (5) IN (4) ON/OFF OUT V5 R1 R2 COMP Bandgap Reference VCC VCC PIN FUNCTION DESCRIPTIONS Pin # Symbol Pin Description 1 OUT This signal drives the gate of a P−channel MOSFET. It is controlled by the voltage level on IN or the logic state of the CNTRL input. When an overvoltage event is detected, the OUT pin is driven to within 1.0 V of VCC in less than 1.0 msec provided that gate and stray capacitance is less than 12 nF. 2 GND Circuit Ground 3 CNTRL This logic signal is used to control the state of OUT and turn−on/off the P−channel MOSFET. A logic High results in the OUT signal being driven to within 1.0 V of VCC which disconnects the FET. The input is tied Low via an internal 50 k W pull−down resistor. It is recommended that the input be connected to GND if it is not used. 4 IN This pin senses an external voltage point. If the voltage on this input rises above the overvoltage threshold (Vth), the OUT pin will be driven to within 1.0 V of VCC, thus disconnecting the FET. The nominal threshold level can be increased with the addition of an external resistor divider between IN, VCC, and GND. 5 VCC Positive Voltage supply. OUT is guaranteed to be in low state (MOSFET ON) as long as VCC remains above 2.5 V, and below the overvoltage threshold. TRUTH TABLE IN CNTRL OUT <Vth L GND <Vth H VCC >Vth L VCC >Vth H VCC |
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