NCP345

http://onsemi.com

2

Figure 2. Detailed Block Diagram

−

+

CNTRL

(3)

OUT

(1)

GND

(2)

−

+

LOGIC

BLOCK

DRIVER

Pre−

regulator

(5)

IN

(4)

ON/OFF

UVLO

OUT

V5

R1

R2

R3

R4

COMP

Bandgap

Reference

PIN FUNCTION DESCRIPTIONS

Pin #

Symbol

Pin Description

1

OUT

This signal drives the gate of a P−channel MOSFET. It is controlled by the voltage level on IN or the logic state

less than 1.0

msec provided that gate and stray capacitance is less than 12 nF.

2

GND

Circuit Ground

3

CNTRL

This logic signal is used to control the state of OUT and turn−on/off the P−channel MOSFET. A logic High

the input should be connected to ground.

4

IN

This pin senses an external voltage point. If the voltage on this input rises above the overvoltage threshold

level is 6.85 V and this threshold level can be increased with the addition of an external resistor between IN

5

disconnecting the P−channel FET.

TRUTH TABLE

IN

CNTRL

OUT

L

GND

H

L

H