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NBSG86A Datasheet(PDF) 9 Page - ON Semiconductor

Part # NBSG86A
Description  2.5V/3.3V SiGe Differential Smart Gate with Output Level Select
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NBSG86A Datasheet(HTML) 9 Page - ON Semiconductor

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NBSG86A
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Table 13. AC CHARACTERISTICS for FCBGA−16
VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
Symbol
Characteristic
−40
°C
25
°C
70
°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency
(See Figure 8) (Note 25)
7
8
7
8
7
8
GHz
VOUTPP
Output Voltage Amplitude
(OLS = VCC)fin v 7 GHz
550
740
500
720
450
700
mV
tPLH,
tPHL
Propagation Delay to Output Differential
D/SEL
→ Q
110
160
210
115
165
215
120
170
220
ps
tSKEW
Duty Cycle Skew (Note 26)
5
15
5
15
5
15
ps
tSKEW
Channel Skew
Q
→ D/SEL
5
20
5
20
5
20
ps
tJITTER
RMS Random Clock Jitter
(See Figure 8) (Note 25)
fin v 7 GHz
Peak−to−Peak Data Dependent Jitter
fin v 7 Gb/s
0.5
12
1.5
0.5
12
1.5
0.5
12
1.5
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 27)
75
2600
75
2600
75
2600
mV
tr
tf
Output Rise/Fall Times (20% − 80%)
(Q, Q)
@ 1 GHz
20
40
65
20
40
65
20
40
65
ps
25. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50
W to VCC − 2.0 V. Input edge rates 40 ps (20% − 80%).
26. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform. See Figure 12.
27. VINPP (max) cannot exceed VCC − VEE.
Table 14. AC CHARACTERISTICS for QFN−16
VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
Symbol
Characteristic
−40
°C
25
°C
85
°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency
(See Figure 8) (Note 28)
7
8
7
8
7
8
GHz
VOUTPP
Output Voltage Amplitude
fin v 7 GHz
(OLS = VCC)fin = 8 GHz
590
270
730
440
470
230
720
420
540
180
700
390
mV
mV
tPLH,
tPHL
Propagation Delay to Output Differential
D/SEL
→ Q
110
160
210
115
165
215
120
170
220
ps
tSKEW
Duty Cycle Skew (Note 29)
5
15
5
15
5
15
ps
tSKEW
Channel Skew
Q
→ D/SEL
5
20
5
20
5
20
ps
tJITTER
RMS Random Clock Jitter
(See Figure 8) (Note 31)
fin v 7 GHz
Peak−to−Peak Data Dependent Jitter
(Note 32)
fin v 7 Gb/s
0.5
12
1.5
0.5
12
1.5
0.5
12
1.5
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 30)
75
2600
75
2600
75
2600
mV
tr
tf
Output Rise/Fall Times (20% − 80%)
(Q, Q)
tr
@ 1 GHz
tf
30
17
45
35
60
65
30
17
45
35
60
65
30
17
45
35
60
65
ps
28. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50
W to VCC − 2.0 V. Input edge rates 40 ps (20% − 80%).
29. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform. See Figure 12.
30. VINPP (max) cannot exceed VCC − VEE.
31. Additive RMS jitter with 50% duty cycle clock signal at 7 GHz.
32. Additive Peak−to−Peak data dependent jitter with NRZ PRBS 231−1 data rate at 7 Gb/s.


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