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NB4N855S Datasheet(PDF) 5 Page - ON Semiconductor

Part No. NB4N855S
Description  3.3 V, 1.5 Gb/s Dual AnyLevel TM to LVDS Receiver/Driver/Buffer/ Translator
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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NB4N855S Datasheet(HTML) 5 Page - ON Semiconductor

   
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NB4N855S
http://onsemi.com
5
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; (Note 9)
Symbol
Characteristic
−40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOUTPP Output Voltage Amplitude (@ VINPPMIN)fin ≤ 1.0 GHz
(Figure 3)
fin= 1.5 GHz
230
200
350
300
230
200
350
300
230
200
350
300
mV
fDATA
Maximum Operating Data Rate
1.5
2.5
1.5
2.5
1.5
2.5
Gb/s
tPLH,
tPHL
Differential Input to Differential Output
Propagation Delay
330
410
490
330
410
490
330
410
490
ps
tSKEW
Duty Cycle Skew (Note 10)
Within −Device Skew (Note 11)
Device to Device Skew (Note 12)
8
10
20
45
35
100
8
10
20
45
35
100
8
10
20
45
35
100
ps
tJITTER
RMS Random Clock Jitter (Note 13)
fin = 1.0 GHz
fin = 1.5 GHz
Deterministic Jitter (Note 14)
fDATA = 622 Mb/s
fDATA = 1.5 Gb/s
fDATA = 2.488 Gb/s
Crosstalk Induced Jitter (Note 15)
0.5
0.5
6
7
10
20
1
1
15
20
25
40
0.5
0.5
6
7
10
20
1
1
15
20
25
40
0.5
0.5
6
7
10
20
1
1
15
20
25
40
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 16)
100
VCC
GND
100
VCC
GND
100
VCC
GND
mV
tr
tf
Output Rise/Fall Times @ 250 MHz
Q, Q
(20% − 80%)
50
110
180
50
110
180
50
110
180
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing VINPPMIN with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W across
“D” and “D” of the receiver. Input edge rates 150 ps (20%−80%).
10.See Figure 7 differential measurement of tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform @ 250 MHz.
11. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
12.Skew is measured between outputs under identical transition @ 250 MHz.
13.RMS jitter with 50% Duty Cycle clock signal.
14.Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5.
15.Crosstalk Induced Jitter is the additive Deterministic jitter to channel one with channel two active both running at 622 Gb/s PRBS 223 −1 as
an asynchronous signals.
16.Input voltage swing is a single−ended measurement operating in differential mode.
INPUT CLOCK FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V)
0
50
100
150
200
250
300
350
400
0.5
1
1.5
2
2.5
3
0
85°C
−40°C
25°C


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