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MC9S08RD60CFDE Datasheet(PDF) 61 Page - Freescale Semiconductor, Inc |
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MC9S08RD60CFDE Datasheet(HTML) 61 Page - Freescale Semiconductor, Inc |
61 / 234 page Resets, Interrupts, and System Configuration MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 61 5.5.2.2 Edge and Level Sensitivity The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In this edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared) as long as the IRQ pin remains at the asserted level. 5.5.3 Interrupt Vectors, Sources, and Local Masks Table 5-1 provides a summary of all interrupt sources. Higher-priority sources are located towards the bottom of the table. The high-order byte of the address for the interrupt service routine is located at the first address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the next higher address. When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in the CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. |
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