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MC9S08RD60DWE Datasheet(PDF) 57 Page - Freescale Semiconductor, Inc

Part # MC9S08RD60DWE
Description  Microcontrollers
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MC9S08RD60DWE Datasheet(HTML) 57 Page - Freescale Semiconductor, Inc

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MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
57
Chapter 5
Resets, Interrupts, and System Configuration
5.1
Introduction
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts
in the MC9S08RC/RD/RE/RG. Some interrupt sources from peripheral modules are discussed in greater
detail within other sections of this data sheet. This section gathers basic information about all reset and
interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer
operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral
systems having their own sections but are part of the system control logic.
5.2
Features
Reset and interrupt features include:
Multiple sources of reset for flexible system configuration and reliable operation:
— Power-on detection (POR)
— Low voltage detection (LVD) with enable
— External reset pin with enable (RESET)
— COP watchdog with enable and two timeout choices
— Illegal opcode
— Illegal address (on 16K and 8K devices)
— Serial command from a background debug host
Reset status register (SRS) to indicate source of most recent reset; flag to indicate stop2 (partial
power down) mode recovery (PPDF)
Separate interrupt vectors for each module (reduces polling overhead) (see Table 5-1)
Safe state for protecting the MCU in low-voltage condition
5.3
MCU Reset
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is loaded from the
reset vector ($FFFE:$FFFF). On-chip peripheral modules are disabled and I/O pins are initially configured
as general-purpose high-impedance inputs with pullup devices disabled. The I bit in the condition code
register (CCR) is set to block maskable interrupts until the user program has a chance to initialize the stack
pointer (SP) and system control settings. SP is forced to $00FF at reset.


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