ZL50075 datasheet(24/60 Pages) ZARLINK

Part #	ZL50075

Description	32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Streams (8, 16, 32 or 64 Mbps), and 64 Inputs and 64 Outputs

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Manufacturer	ZARLINK [Zarlink Semiconductor Inc]

Direct Link	http://www.zarlink.com

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ZL50075

Data Sheet

24

Zarlink Semiconductor Inc.

The Address Bus, A18 - 0, controls access to each 32 bit location. A0 is not used and must be connected to defined

logic level. Address bit A1 and the Data Transfer Size inputs, SIZ1 - 0, identify which bytes are being accessed.

In Motorola Bus Mode (IM = 0), SIZ1 - 0 form active low data strobe signals, consistent with UDS and LDS available

on the MC68000 and MC68302 processors, as shown in Table 6.

In Intel Bus Mode (IM = 1), SIZ1 - 0 form active low byte enable signals, consistent with BE1 and BE0 available on

the Intel i960 processor, as shown in Table 6.

In both Intel and Motorola modes, the A1 address input is used to identify the word alignment in internal memory, as

shown in Table 7.

Data bus word alignments are shown in Table 8. An example of byte addressing is given in Table 9.

Address (Hex)

Memory/Register Bits

40200

Bits 31:24 (MSB)

40201

Bits 23:16

40202

Bits 15:8

40203

Bits 7:0 (LSB)

Table 5 - Example of Address and Byte Significance

Pin Name

Motorola Mode MC68000, MC68302

Equivalent Function

IM = 0

Intel Mode i960

Equivalent Function

IM = 1

Data Bus Bytes Enabled

SIZ1

UDS

BE1

D15-8

SIZ0

LDS

BE0

D7-0

Table 6 - Byte Enable Signals

A1

Memory Data Word Alignment

0Bits 31:16

1

Bits 15:0

Table 7 - Memory Data Word Alignment

Microprocessor

16 Bit Data Bus

SIZ1

SIZ0

A1

Internal 32-Bit Memory

or Register

D15 - 8

0

1

0

Bits 31:24

01

1

Bits 15:8

D7 - 0

1

0

Bits 23:16

10

1

Bits 7:0

D15 - 0

0

Bits 31:16

00

1

Bits 15:0

11

X1

1. X - Don’t Care

No access

Table 8 - Data Bus Word Alignment

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