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ZL50075 Datasheet(PDF) 43 Page - Zarlink Semiconductor Inc |
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ZL50075 Datasheet(HTML) 43 Page - Zarlink Semiconductor Inc |
43 / 60 page ZL50075 Data Sheet 43 Zarlink Semiconductor Inc. 14.6 Output Clock Control Register The Output Clock Control Register is used to select the desired source, frequency, and logic sense of the output clocks. The bit functions of the Output Clock Control Register are illustrated in Table 25. Bit Name Description 31 - 28 Unused Reserved. In normal functional mode, these bits MUST be set to zero. 27 - 14 Unused Reserved. In normal functional mode, these bits MUST be set to 01100000110100. 13 GCO SEL1 GCI-Bus Selection for FPo1 When this bit is low, FPo1 is set for ST-BUS mode. When this bit is high, FPo1 is set for GCI-Bus mode. 12 FPO POL1 Frame Pulse Polarity Selection for FPo1 When this bit is low, FPo1 is set for active high. When this bit is high, FPo1 is set for active low. 11 CKO POL1 Clock Polarity Selection for CKo1 When this bit is low, CKo1 is set for the positive clock edge. When this bit is high, CKo1 is set for the negative clock edge. 10 - 9 CKO1 RATE 1 - 0 Output Clock Rate for CKo1 and FPo1 The output clock rate can not exceed the selected clock source rate. All rates are avail- able when the internal system clock is selected as clock source. 8 - 7 CKO1 SRC 1 - 0 Output Clock Source for CKo1 and FPo1 Table 25 - Output Clock Control Register External Read/Write Address: 40284H Reset Value: 060D1C3CH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 000 1 1 0 0 0 0 0 1 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 GCO SEL1 FPO POL1 CKO POL1 CKO1 RATE1 CKO1 RATE0 CKO1 SRC1 CKO1 SRC0 GCO SEL0 FPO POL0 CKO POL0 CKO0 RATE1 CKO0 RATE0 CKO0 SRC1 CKO0 SRC0 CKO1RATE1 - 0 CKo1FPo1 00 8.192 MHz 120 ns 01 16.384 MHz 60 ns 10 32.768 MHz 30 ns 11 65.536 MHz 15 ns CKO1SRC1 - 0 Output Timing Source 00 Internal System Clock 01 CKi0 and FPi0 10 Reserved 11 Reserved |
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