ZL50075 datasheet(42/60 Pages) ZARLINK

Part #	ZL50075

Description	32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Streams (8, 16, 32 or 64 Mbps), and 64 Inputs and 64 Outputs

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Manufacturer	ZARLINK [Zarlink Semiconductor Inc]

Direct Link	http://www.zarlink.com

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ZL50075

Data Sheet

42

Zarlink Semiconductor Inc.

14.5

Input Clock Control Register

The Input Clock Control Register is used to select the logic sense of the input clock.

Bit

Name

Description

31 - 9

Unused

Reserved. In normal functional mode, these bits MUST be set to zero.

8 - 3

Unused

Reserved. In normal functional mode, these bits MUST be set to 011011.

2

GCISEL0

GCI-Bus Selection for FPi0

When this bit is low, FPi0 is set for ST-BUS mode.

When this bit is high, FPi0 is set for GCI-Bus mode.

1

FPIPOL0

Frame Pulse Polarity Selection for FPi0

When this bit is low, FPi0 is set for active high.

When this bit is high, FPi0 is set for active low.

0CKIPOL0

Clock Polarity Selection for CKi0

When this bit is low, CKi0 is set for the positive clock edge.

When this bit is high, CKi0 is set for the negative clock edge.

Table 24 - Input Clock Control Register

External Read/Write Address: 40280H

Reset Value: 0DBH

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

00

0

000

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

00

0

000

0

1

0

1

GCI

SEL0

FPI

POL0

CKI

POL0

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ZL50075 Datasheet(PDF) 42 Page - Zarlink Semiconductor Inc

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