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ZL50073 Datasheet(PDF) 46 Page - Zarlink Semiconductor Inc

Part No. ZL50073
Description  32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 128 Inputs and 128 Outputs
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Maker  ZARLINK [Zarlink Semiconductor Inc]
Homepage  http://www.zarlink.com
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ZL50073
Data Sheet
46
Zarlink Semiconductor Inc.
The Group Control Register is a static control register. Changes to bit settings may disrupt data flow on the selected
port for a maximum of 2 frames.
3 - 2
ISBR1 - 0
Input Stream Bit Rate
Unused streams must be connected to ground.
If the internal system clock is used as the clock source, all the above data rates are
available. Otherwise, the data rate cannot exceed the selected clock source’s rate.
1 - 0
ISSRC1 - 0
Input Stream Clock Source Select
Bit
Name
Description
Table 25 - Group Control Register (continued)
External Read/Write Address: 40200H - 4027FH
Reset Value: 000C000CH
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
OSI
OSBA 1 OSBA 0 OSBR 1
OSBR 0
OSSRC 1
OSSRC 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
ISI
ISPD
4
ISPD
3
ISPD
2
ISPD
1
ISPD
0
ISBR
1
ISBR
0
ISSRC
1
ISSRC
0
ISBR1 - 0
Bit Rates Per Group
STi/oA
STi/oB
STi/oC
STi/oD
00
8.192 Mbps
8.192 Mbps
8.192 Mbps
8.192 Mbps
01
16.384 Mbps
16.384 Mbps
16.384 Mbps
16.384 Mbps
10
32.768 Mbps
32.768 Mbps
Not Used
Not Used
11
65.536 Mbps
Not Used
Not Used
Not Used
ISSRC1 - 0
Input Timing Source
00
Internal System Clock
01
CKi0 and FPi0
10
CKi1 and FPi1
11
CKi2 and FPi2




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