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MC9S08RD60 Datasheet(PDF) 27 Page - Freescale Semiconductor, Inc |
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MC9S08RD60 Datasheet(HTML) 27 Page - Freescale Semiconductor, Inc |
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27 / 234 page  Pins and Connections MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 27 PTD2/IRQ I/O N SWC(5) Available only in 32-, 44-, and 48-pin packagess PTD3 I/O N SWC Available only in 44- and 48-pin packages PTD4/ACMP1– I/O N SWC Available only in 32-, 44-, and 48-pin packagess PTD5/ACMP1+ I/O N SWC Available only in 32-, 44-, and 48-pin packagess PTD6/TPM1CH0 I/O N SWC PTE0 I/O N SWC Available only in 44- and 48-pin packages PTE1 I/O N SWC Available only in 44- and 48-pin packages PTE2 I/O N SWC Available only in 44- and 48-pin packages PTE3 I/O N SWC Available only in 44- and 48-pin packages PTE4 I/O N SWC Available only in 44- and 48-pin packages PTE5 I/O N SWC Available only in 44- and 48-pin packages PTE6 I/O N SWC Available only in 44- and 48-pin packages PTE7 I/O N SWC Available only in 44- and 48-pin packages 1. Unless otherwise indicated, all digital inputs have input hysteresis. 2. SWC is software-controlled pullup resistor, the register is associated with the respective port. 3. Not all general-purpose I/O pins are available on all packages. To avoid extra current drain from floating input pins, the user’s reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unconnected pins to outputs so the pins do not float. 4. When these pins are configured as RESET or BKGD/MS pullup device is enabled. 5. When configured for the IRQ function, this pin will have a pullup device enabled when the IRQ is set for falling edge detection and a pulldown device enabled when the IRQ is set for rising edge detection. Table 2-2. Signal Properties (continued) Pin Name Dir(1) High Current Pin Pullup(2) Comments(3) |
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Similar Description - MC9S08RD60 |
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