CAT93C46

3

Doc No. 1106, Rev. F

© 2007 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

Limits

Symbol

Parameter

Min

Max

Units

CS Setup Time

50

ns

CS Hold Time

0

ns

DI Setup Time

100

ns

DI Hold Time

100

ns

Output Delay to 1

0.25

µs

Output Delay to 0

0.25

µs

Output Delay to High-Z

100

ns

Program/Erase Pulse Width

5

ms

Minimum CS Low Time

0.25

µs

Minimum SK High Time

0.25

µs

Minimum SK Low Time

0.25

µs

Output Delay to Status Valid

0.25

µs

Maximum Clock Frequency

DC

2000

kHz

PIN CAPACITANCE

Symbol

Test

Conditions

Min

Typ

Max

Units

Output Capacitance (DO)

5

pF

Input Capacitance (CS, SK, DI, ORG)

5

pF

NOTES:

(1) These parameters are tested initially and after a design or process change that affects the parameter according to

appropriate AEC-Q100 and JEDEC test methods.

(2) Test conditions according to “AC Test Conditions” table.

Symbol

Parameter

Max

Units

Power-up to Read Operation

1

ms

Power-up to Write Operation

1

ms