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CAT93C46VP2IT2 Datasheet(PDF) 3 Page - Catalyst Semiconductor |
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CAT93C46VP2IT2 Datasheet(HTML) 3 Page - Catalyst Semiconductor |
3 / 15 page CAT93C46 3 Doc No. 1106, Rev. F © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Limits Symbol Parameter Min Max Units tCSS CS Setup Time 50 ns tCSH CS Hold Time 0 ns tDIS DI Setup Time 100 ns tDIH DI Hold Time 100 ns tPD1 Output Delay to 1 0.25 µs tPD0 Output Delay to 0 0.25 µs tHZ(1) Output Delay to High-Z 100 ns tEW Program/Erase Pulse Width 5 ms tCSMIN Minimum CS Low Time 0.25 µs tSKHI Minimum SK High Time 0.25 µs tSKLOW Minimum SK Low Time 0.25 µs tSV Output Delay to Status Valid 0.25 µs SKMAX Maximum Clock Frequency DC 2000 kHz A.C. CHARACTERISTICS(2) VCC = +1.8V to +5.5V, TA=-40°C to +85°C, unless otherwise specified. PIN CAPACITANCE TA=25°C, f=1MHz, VCC=5V Symbol Test Conditions Min Typ Max Units COUT(1) Output Capacitance (DO) VOUT=0V 5 pF CIN(1) Input Capacitance (CS, SK, DI, ORG) VIN=0V 5 pF NOTES: (1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (2) Test conditions according to “AC Test Conditions” table. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. POWER-UP TIMING (1)(3) Symbol Parameter Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms |
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