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MC100LVEP111FA Datasheet(PDF) 1 Page - ON Semiconductor |
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MC100LVEP111FA Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 10 page © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 13 1 Publication Order Number: MC100LVEP111/D MC100LVEP111 2.5V / 3.3V1:10 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when the LVEP111 is operating under PECL conditions. The LVEP111 specifically guarantees low output−to−output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure tightest skew, both sides of differential outputs identically terminate into 50 W even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. The MC100LVEP111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVEP111 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. Single−ended CLK input operation is limited to a VCC ≥ 3.0 V in PECL mode, or VEE v −3.0 V in NECL mode. Designers can take advantage of the LVEP111’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Application Note AN1406/D. Features • 85 ps Typical Device−to−Device Skew • 20 ps Typical Output−to−Output Skew • Jitter Less than 1 ps RMS • Maximum Frequency > 3 Ghz Typical • VBB Output • 430 ps Typical Propagation Delay • The 100 Series Contains Temperature Compensation • PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −2.375 V to −3.8 V • Open Input Default State • LVDS Input Compatible • Fully Compatible with MC100EP111 • Pb−Free Packages are Available 32 1 LQFP−32 FA SUFFIX CASE 873A MARKING DIAGRAM* MC100 AWLYYWWG LVEP111 http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ORDERING INFORMATION A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G= Pb−Free Package QFN32 MN SUFFIX CASE 488AM 32 1 MC100 LVEP111 ALYWG 1 |
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