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MC100LVEL39 Datasheet(PDF) 2 Page - ON Semiconductor

Part No. MC100LVEL39
Description  3.3V ECL ÷2/4, ÷4/6 Clock Generation Chip
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC100LVEL39 Datasheet(HTML) 2 Page - ON Semiconductor

   
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MC100LVEL39
http://onsemi.com
2
CLK
CLK
MR
VCC
17
18
16
15
14
13
12
4
3
5678
9
Q0
11
10
Q1
Q1
Q2
Q2
Q3
Q3
VEE
EN
19
20
2
1
VCC
Q0
DIVSELb
VBB
VCC
NC DIVSELa
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. Pinout: SOIC−20 (Top View)
CLK
CLK
EN
MR
DIVSELb
÷
2/4
Q0
Q0
Q1
Q1
÷
4/6
Q2
Q2
Q3
Q3
R
R
DIVSELa
VBB
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
Column Head
CLK, CLK
Q0, Q1; Q0, Q1
Q2, Q3; Q2, Q3
DIVSELa, DIVSELb
EN
MR
VBB
VCC
VEE
NC
ECL Diff Clock Inputs
ECL Diff ÷2/4 Outputs
ECL Diff ÷4/6 Outputs
ECL Frequency Select Inputs
ECL Sync Enable
ECL Master Reset
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
Table 2. FUNCTION TABLE
CLK
EN
MR
Function
Z
ZZ
X
L
H
X
L
L
H
Divide
Hold Q0−3
Reset Qo−3
Z = Low-to-High Transition
ZZ = High-to-Low Transition
X = Don’t Care
DIVSELa
Q0, Q1 Outputs
L
H
Divide by 2
Divide by 4
DIVSELb
Q2, Q3 Outputs
L
H
Divide by 4
Divide by 6
CLK
Q (÷2)
Q (÷4)
Q (÷6)
Figure 3. Timing Diagrams


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