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MC100LVEL38 Datasheet(PDF) 2 Page - ON Semiconductor

Part No. MC100LVEL38
Description  3.3V ECL ÷2, ÷4/6 Clock Generation Chip
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC100LVEL38 Datasheet(HTML) 2 Page - ON Semiconductor

   
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MC100LVEL38
http://onsemi.com
2
CLK
Figure 1. Pinout: 20-Lead SOIC (Top View)
CLK
MR VCC
17
18
16
15
14
13
12
4
3
5678
9
Q0
11
10
Q1
Q1
Q2
Q2
Q3
Q3
VEE
EN
19
20
2
1
VCC
Q0
DIV_SEL
VBB
VCC
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Phase_Out
Phase_Out
Phase
Out
Logic
CLK
CLK
EN
MR
DIVSEL
÷2
Q0
Q0
Q1
Q1
÷4/6
Q2
Q2
Q3
Q3
PHASE_OUT
PHASE_OUT
Figure 2. Logic Diagram
R
R
R
R
VBB
Table 1. PIN DESCRIPTION
Pin
Function
CLK, CLK
ECL Diff Clock Inputs
Q0, Q1; Q0, Q1
ECL Diff ÷2 Outputs
Q2, Q3; Q2, Q3
ECL Diff ÷4/6 Outputs
EN
ECL Sync Enable Input
MR
ECL Master Reset Input
DIVSEL
ECL Frequency Select Input
Phase_Out, Phase_Out
ECL Phase Sync Diff. Signal Output
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
Table 2. FUNCTION TABLE
CLK
EN
MR
Function
Z
ZZ
X
L
H
X
L
L
H
Divide
Hold Q0−3
Reset Q0−3
Z = Low-to-High Transition
ZZ = High-to-Low Transition
X = Don’t Care
DVSEL
Q2, Q3 OUTPUTS
L
H
Divide by 4
Divide by 6


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