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MC100LVEL38 Datasheet(PDF) 1 Page - ON Semiconductor

Part No. MC100LVEL38
Description  3.3V ECL ÷2, ÷4/6 Clock Generation Chip
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com

MC100LVEL38 Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 8
Publication Order Number:
3.3VECL ÷2, ÷4/6 Clock
Generation Chip
The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either a
differential or single-ended input signal.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as can happen with an
asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
The Phase_Out output will go HIGH for one clock cycle whenever
the ÷2 and the ÷4/6 outputs are both transitioning from a LOW to a
HIGH. This output allows for clock synchronization within the system.
Upon startup, the internal flip-flops will attain a random state; therefore,
for systems which utilize multiple LVEL38s, the master reset (MR) input
must be asserted to ensure synchronization. For systems which only use
one LVEL38, the MR pin need not be exercised as the internal divider
design ensures synchronization between the ÷2 and the ÷4/6 outputs of a
single device.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
50 ps Maximum Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
ESD Protection: >2 kV Human Body Model
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range:
VCC = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −3.8 V
Internal Input 75 kW Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 388 devices
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional marking information, refer to
Application Note AND8002/D.
= Assembly Location
= Wafer Lot
= Year
= Work Week
G= Pb−Free Package
SO−20 WB

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