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CAT25C04VITE13 Datasheet(PDF) 7 Page - Catalyst Semiconductor

Part # CAT25C04VITE13
Description  1K/2K/4K SPI Serial CMOS EEPROM
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Manufacturer  CATALYST [Catalyst Semiconductor]
Direct Link  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT25C04VITE13 Datasheet(HTML) 7 Page - Catalyst Semiconductor

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Discontinued
Parts
7
CAT25C01, CAT25C02, CAT25C04
Doc. No. 1105, Rev. B
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 4. Read Instruction Timing
Figure 5. RDSR Instruction Timing
Note: Dashed Line= mode (1, 1) – ––––
21
22
SK
SI
SO
0000001
1
BYTE ADDRESS
0123456789
10
12
13
14
15
16
17
18
19
20
D7 D6 D5 D4 D3 D2 D1 D0
*Please check the instruction set table for address
CS
OPCODE
DATA OUT
MSB
HIGH IMPEDANCE
11
A7
A6
A5
A4
A3
A2
A1 A0
X=0 for 25010, 25020 ; X=A8 for 25040
Note: Dashed line = mode (1,1)----
X*
0
1
2
345
67
8
10
911
12
13
14
SCK
SI
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
SO
7
6
5
4
3
2
1
0
CS
00
0
00
1
0
1
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continuing
to provide clock pulses. The internal address pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000h allowing the read cycle to be continued indefinitely.
The read operation is terminated by pulling the
CS high.
To read the status register, RDSR instruction should
be sent. The contents of the status register are shifted
out on the SO line. The status register may be read at
any time even during a write cycle. Read sequece is
illustrated in Figure 4. Reading status register is illustrated
in Figure 5.
WRITE Sequence
The CAT25C01/02/04 powers up in a Write Disable
state. Prior to any write instructions, the WREN instruction
must be sent to CAT25C01/02/04. The device goes into
Write enable state by pulling the
CS low and then
clocking the WREN instruction into CAT25C01/02/04.
The
CS must be brought high after the WREN instruction
to enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the
CS low,
issuing a write instruction via the SI line, followed by the
8-bit address for CAT25C01/02/04 (for the 25C04, bit 3
of the read data instruction contains address A8).
Programming will start after the
CS is brought high.
Figure 6 illustrates byte write sequence.


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